The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of changing the sequence in which data is input in a test mode to enhance an ability to screen the data.
FIG. 1 is a block diagram of a typical semiconductor memory device for aligning received data for transfer to data input/output lines.
Referring to FIG. 1, the typical semiconductor memory device includes an input buffer unit 110, an alignment unit 120, a matching unit 130, and a driver unit 140 to receive data DQ_I at a data pin DQ and transfer the received data to data input/output lines GIO0 to GIO7.
The input buffer 110 buffers data input in series through the data pin DQ.
The alignment unit 120 aligns the serial input data DQ_I in parallel using rising and falling data strobe signals DQSR and DQSF. The data D0 to D7 are input in series according to a burst length (BL). FIG. 1 illustrates the case where the BL is 8. Accordingly, when eight data are input in a sequence of D0, D1, D2, D3, D4, D5, D6 and D7, the data are aligned as follows: D0=ALIGNR_0 D1=ALIGNF_0 D2=ALIGNR_1, D3=ALIGNF_1, D4=ALIGNR_2, D5=ALIGNF_2, D6=ALIGNR_3 and D7=ALIGNF_3.
Basically, the matching unit 130 matches the lines ALIGNR_0, ALIGNR_1, ALIGNR_2 and ALIGNR_3 to the lines ALIGNRD_0, ALIGNRD_1, ALIGNR_2 and ALIGNRD_3 and the lines ALIGNF_0, ALIGNF_1, ALIGNF_2 and ALIGNF_3 to the lines ALIGNFD_0, ALIGNFD_1, ALIGNFD_2 and ALIGNFD_3, respectively, in the above-listed sequences (note that BL=8 basically in a DDR3 memory device as shown in FIG. 1). Therefore, the data D0 to D7 are sequentially loaded on the input/output lines GIO0 to GIO7.
When the BL is 4 (i.e., a signal BL4 is activated), the matching unit 130 transfers the data from the lines ALIGN_2 and ALIGN_3 to the lines ALIGNED_0 and ALIGNED_1 (hereinafter, ALIGN represents both ALIGNR and ALIGNF, and ALIGNED represents both ALIGNRD and ALIGNFD), whereas it transfers the data from the lines ALIGN_0 and ALIGN_1 to the lines ALIGNED_0 and ALIGNED_1 respectively, in the above-listed sequences. Accordingly, four data D0, D1, D2 and D3 input thereinto according to the BL are sequentially loaded on the input/output lines GIO0, GIO1, GIO2 and GIO3, respectively, in the above-listed sequence. In an on-the-fly mode (i.e., a signal BLFLYB is at a logic low level), the matching unit 130 transfers data from the lines ALIGN_0 and ALIGN_1 to the lines ALIGNED_2 and ALIGNED_3, whereas it transfers data from the lines ALIGN_0 and ALIGN_1 to the lines ALIGNED_0 ALIGNED_1 in the above-listed sequences. Accordingly, the four data D0, D1, D2 and D3 input thereinto are sequentially loaded on the input/output lines GIO4, GIO5, GIO6 and GIO7, respectively, in the above-listed sequence.
The matching unit 130 is provided to the memory device to support burst lengths other than the basic burst length. For example, a DDR3 memory device as shown in FIG. 1 may be provided with the matching unit for supporting the burst length of 4 and the on-the-fly mode as well as the burst length of 8. Accordingly, in a case where only one burst length is used, the memory device may not include the matching unit 130.
FIG. 2 is a circuit diagram of the matching unit 130 of the typical semiconductor memory device shown in FIG. 1.
Referring to FIG. 2, the typical matching unit 130 includes a plurality of multiplexers 210, 220, 230 and 240 each of which selects one of two signals (data) according to the signal BL4 or the signal BLFLYB. The symbols of R and F are omitted in FIG. 2 because the line ALIGNR and the line ALIGNF has the same configuration as the line ALIGN shown in FIG. 2. Therefore, the matching unit 130 of FIG. 1 includes two of the circuit shown in FIG. 2 (i.e., eight multiplexers).
When BL=8, and both of the signal BL4 and the signal BLFLYB are deactivated (i.e., the signal BL4 is at a logic low level, and the signal BLFLYB is at a logic high level), the lines ALIGN_0, ALIGN_1, ALIGN_2 and ALIGN_3 are matched to the lines ALIGNED_0, ALIGNED_1, ALIGNED_2 and ALIGNED_3, respectively, in the above-listed sequence.
When BL=4, and the signal BL4 is activated to a logic high level the lines ALIGN_2 and ALIGN_3 may be matched to the lines ALIGNED_0 and ALIGNED_1 and may also be matched to the lines ALIGNED_2 and ALIGNED_3. However, it doesn't matter because the number of data input at a time is 4, instead of 8 in this case.
In an on-the-fly mode, when the signal BLFLYB is activated to a logic low level, the lines ALIGN_1 and ALIGN_2 may be matched to the lines ALIGNED_2 and ALIGNED_3, and may also be matched to the lines ALIGNED_1 and ALIGNED_2. However, it also doesn't matter because the number of data input at a time is 4, instead of 8, in this mode.
FIG. 3 illustrates an operation of a typical semiconductor memory device for aligning serial input data in parallel for transfer to data input/output lines.
Referring to FIG. 3 (showing the case of BL=8), the semiconductor memory device aligns the serial input data in parallel to output the aligned data to data input/output lines GIO0 to GIO7 in the sequence of their input.
FIG. 3 shows the case where data are input into the memory device by a testing apparatus. Note that in FIG. 3 data D0, D1, D2 and D3 have a logic high level and data D4, D5, D6 and D7 have a logic low level. This represents the case where the data input/output speed of the memory device (for example, 800 MHz) is four times faster than that of the testing apparatus (for example, 200 MHz), and thus the testing apparatus can change the logic levels of the data by the unit of four data (for example, the data D0 to D3, and the data D4 to D7, respectively).
With the development of the technology, the operating speed of the semiconductor memory device is increasing. However, memory manufacturer would not change the testing apparatus immediately to meet the increased operating speed. This is because of the increase of manufacturing cost. Therefore, in a test mode, it could happen that a string of data (for example, D0, D1, D2 and D3) are input into the semiconductor memory device to have the same logic level. Generally, in the test mode, various data patterns are used to detect various defects efficiently. In order to realize various data patterns, it is required to write desired data at desired location. Therefore, there are occasions where a string of data must have different logic levels (for example, D0 has a logic high level, D1 has a logic low level, D2 has a logic high level, and D3 has a logic low level).
However, when the testing apparatus is slower than the memory device as shown in FIG. 3, it is difficult to realize various data patterns freely. As a result, the ability to screen to detect various defects in the memory device may be reduced.